The Journey to PHD in Engineering

Conventional tunnel oxide and ONO interpoly limit the scalability of Flash Memory towards the 45nm node and beyond. Reduced tunnel oxide thickness will lower down the programming voltage as desired but the data retention capability will be severely compromised.

One of the proposed solutions include the use of engineered tunnel barrier by means of high-k materials. Two main engineered tunnel barriers proposed are;

a) Crested Barrier - Crested Tunnel Barrier

b) Variot Stack -

Up to this point, the major problem with the proposed structure was the efficient tunneling only happened in one direction, which is not suitable for NAND-type memory cell.

This paper demonstrate the operation of memory cells with bidirectional engineered tunnel barrier, using a triple layer Variot stack.

Device Structure

Three layer Variot as tunnel dielectric - 2nm thermal oxide / 8nm Al2O3 / post deposition annealing in N2 for 1 minute @ 800C / 2nm HTO

Result

Drastic decrease in programming voltage (9V for program and erase), as compared to 16-19V using conventional tunnel oxide.

One major problem is the charge trapping capability in Al2O3 will limit the endurance i.e program cycle of memory cells.

This work suggest that Al2O3 is a suitable dielectric materials for both tunnel and IPD in floating gate Flash memory.

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A Nonvolatile Memory Overview

Posted in Articles, General on November 13, 2007 by ramzannvm

By Jitu J.Makmawa, Dr Deiter K.Schroder - Full Paper

Memory devices can be split into two main categories; volatile and nonvolatile. A nonvolatile memory device is a MOS transistor having a source, drain, control and floating gates. Nonvolatile memory cell can be further divided into floating gate Floating Gate Device and charge trapping. Floating gate structure is the most widely used structure in current memory device technology i.e EPROM, EEPROM and Flash.

In both floating gate and charge-trapping memories, the charges needed to program the memory cell, in order to change the memory state or the charge contents of NVM. Two main mechanism is widely used; FN tunneling and Channel Hot Electron Injection. There are two models that can be used to describe the gate current due to hot-electron injection. They are the lucky electron model and the effective electron temperature model.

In FN tunneling, tunnel oxide thickness have to be less than 12 nm whereas in the case of CHEI, the tunnel oxide thickness is not critical.

For the erasing, two commonly used methods are UV emission and FN tunneling. UV emission is currently used for erasing EPROM memory contents while FN tunneling commonly used in EEPROM’s and Flash’s.

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